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publication number s29pl-n_00 revision a amendment 5 issue date june 6, 2007 s29pl-n mirrorbit ? flash family s29pl-n mirrorbit ? flash family cover sheet 29PL256N, s29pl 127n, s29pl129n, 256/128/128 mb (16/8/8 m x 16-bi t) cmos, 3.0 volt-only simultaneous read/write, page-mode flash memory data sheet (preliminary) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary s tatus of this document indicates that product qual- ification has been completed, and that initial production has begun. due to the phases of the manufacturing process that requir e maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. publication number s29pl-n_00 revision a amendment 5 issue date june 6, 2007 general description the spansion family name is the latest generation 3.0-volt page mode read family fabricated using the 110 nm mirrorbit tm flash process technology. these 8-word page-mode flash device s are capable of performing simultaneous read and write operations with zero latency on two separate banks. these devices offer fast page access times of 25 to 30 ns, with corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to operate without wait states. the s29pl129n device of fers the additional feature of dual chip enable inputs (ce1# and ce2#) that allow each half of the memory space to be controlled separately. distinctive characteristics architectural advantages ? 32-word write buffer ? dual chip enable inputs (only for s29pl129n) ? two ce# inputs control selection of each half of the memory space ? single power supply operation ? full voltage range of 2.7 ? 3.6 v read, erase, and program operations for battery-powered applications ? voltage range of 2.7 ? 3.1 v valid for pl-n mcp products ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency switching from write to read operations ? 4-bank sector architecture with top and bottom boot blocks ? 256-word secured silicon sector region ? up to 128 factory-locked words ? up to 128 customer-lockable words ? manufactured on 0.11 m process technology ? data retention of 20 years typical ? cycling endurance of 100,000 cycles per sector typical hardware features ? wp#/acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 32 kword sectors. ?at v ih , allows the use of dyb/ppb sector protection ?at v hh , provides accelerated programming in a factory setting ? dual boot and no boot options ? low v cc write inhibit security features ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method locks combinations of individual sectors to prevent program or erase operations within that sector using a user defined 64-bit password s29pl-n mirrorbit ? flash family 29PL256N, s29pl 127n, s29pl129n, 256/128/128 mb (16/8/8 m x 16-bi t) cmos, 3.0 volt-only simultaneous read/write, page-mode flash memory data sheet (preliminary)
4 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) performance characteristics note typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 10,000 cycles; checkerboard data pattern. read access times (@ 30 pf, industrial temp.) random access time, ns (t acc ) 65 70 page access time, ns (t pac c ) 25 30 max ce# access time, ns (t ce ) 65 70 max oe# access time, ns (t oe ) 25 30 current consumption (typical values) 8-word page read 6 ma simultaneous read/write 65 ma program/erase 25 ma standby 20 a typical program & erase times (typical values) (see note) ty p i c a l wo r d 40 s typical effective word (32 words in buffer) 9.4 s accelerated write buffer program 6 s typical sector erase time (32-kword sector) 300 ms typical sector erase time (128-kword sector) 1.6 s package options s29pl-n vbh064 8.0 x 11.6 mm, 64-ball vbh084 8.0 x 11.6 mm, 84-ball 256 z 129 z 127 z
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 5 data sheet (preliminary) table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. input/output descriptions and logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. connection diagrams /physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 special handling instructions for fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 vbh084, 8.0 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 vbh064, 8 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 specification bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.6 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.7 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.8 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8. advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.2 persistent protection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.3 dynamic protection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.4 persistent protection bit lock bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.6 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.7 hardware data protection methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9. power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3 hardware reset# inpu t operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10. secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1 factory secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.2 customer secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.3 secured silicon sector entry and exit command sequences. . . . . . . . . . . . . . . . . . . . . . . . 52 11. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.6 v cc power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.7 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 12. appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13. common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 7 data sheet (preliminary) figures figure 2.1 logic symbols ? pl256n, pl129n, and pl127n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4.1 connection diagram ? 84-ball fine-pitch ball grid array (s29PL256N) . . . . . . . . . . . . . . . . 12 figure 4.2 physical dimensions ? 84-ball fine-pitch ball gr id array (s29PL256N). . . . . . . . . . . . . . . . 13 figure 4.3 connection diagram ? 64-ball fine-pitch ball grid array (s29pl127n). . . . . . . . . . . . . . . . 14 figure 4.4 connection diagram ? 64-ball fine-pitch ball grid array (s29pl129n). . . . . . . . . . . . . . . . 15 figure 4.5 physical dimensions ? 64-ball fine-pitch ball grid array (s29pl-n). . . . . . . . . . . . . . . . . . . . . . . 16 figure 7.1 single word program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7.2 write buffer programming operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7.3 sector erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7.4 write operation status flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 7.5 simultaneous operation block diagram for s29PL256N and s29pl127n . . . . . . . . . . . . . . 41 figure 7.6 simultaneous operation block diagram for s29pl129n . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 8.1 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 8.2 lock register program algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 11.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 11.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 11.3 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 11.4 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 11.5 v cc power-up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 11.6 read operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 11.7 page read operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 11.8 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 11.9 program operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11.10 accelerated program timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11.11 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 11.12 back-to-back read/write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 11.13 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 11.14 toggle bit timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 11.15 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) tables table 2.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6.1 pl256n sector and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6.2 pl127n sector and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6.3 pl129n sector and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7.1 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7.2 dual chip enable device operatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7.3 word selection within a page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7.4 autoselect codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7.5 autoselect entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7.6 autoselect exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7.7 single word program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7.8 write buffer program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7.9 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7.10 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7.11 erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7.12 erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7.13 program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7.14 program resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7.15 unlock bypass entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7.16 unlock bypass program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7.17 unlock bypass reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7.18 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 7.19 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 8.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 8.2 sector protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 10.1 secured silicon sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 10.2 secured silicon sector entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 10.3 secured silicon sector program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 10.4 secured silicon sector exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 11.1 test specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 12.1 memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 12.2 sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 13.1 cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 13.2 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 13.3 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 13.4 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 9 data sheet (preliminary) 1. ordering information the ordering part number is formed by a valid combination of the following: notes 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading s29 and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29pl 256 n 65 ga w w0 0 packing type 0=tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number (v cc range) w0= 2.7 ? 3.1 v 00 = 2.7 ? 3.6 v temperature range w = wireless (?25c to +85c) package type & material set ga= very thin fine-pitch mcp-compatible bga, lead (pb)-free compliant package gf = very thin fine-pitch mcp-compatible bga,lead (pb)-free package speed option 65 = 65 ns 70 = 70 ns process technology n = 110 nm mirrorbit? technology flash density 256= 256 mb 129= 128 mb (dual ce#) 127= 128 mb (single ce#) product family s29pl = 3.0 volt-only simultaneous read/write, page mode flash memory valid combinations v io range package type (note 2) base ordering part number speed option package type, material, & temperature range model number packing type s29PL256N 65, 70 gaw, gfw w0 0, 2, 3 (note 1) 2.7?3.1v vbh 084 8.0 x 11.6 mm 84 -ball mcp-compatible (fbga) s29pl127n s29pl129n vbh 064 8.0 x 11.6 mm 64 -ball mcp-compatible (fbga)
10 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 2. input/output descriptions and logic symbols table 2.1 identifies the input and output packa ge connections provided on the device. figure 2.1 logic symbols ? pl256n, pl129n, and pl127n table 2.1 input/output descriptions symbol type description a max ? a0 input address bus dq15 ? dq0 i/o 16-bit data inputs/outputs/float ce# input chip enable input oe# input output enable input we# input write enable v ss supply device ground nc not connected pin not connected internally ry/by# output ready/busy output and open drain. when ry/by#= v ih , the device is ready to accept read operations and commands. when ry/by#= v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation. v cc supply device power supply reset# input hardware reset pin ce1#, ce2# input chip enable inputs for s29pl129 device logic symbol ? pl256n and pl127n logic symbol ? pl129n note 1. amax = 23 for the pl256n and 22 for the pl127n. m a x+1 16 am a x?a0 wp#/acc re s et# ce# oe# we# ry/by# dq15 ? dq0 vcc 22 16 dq15 ? dq0 a21 ? a0 wp#/acc re s et# ce1# oe# we# ry/by# ce2# vcc
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 11 data sheet (preliminary) 3. block diagram notes 1. ry/by# is an open drain output. 2. a max = a23 (pl256n), a22 (pl127n), a21 (pl129n). 3. pl129n has two ce# pins ce1# and ce2#. v cc v ss s t a te control comm a nd regi s ter pgm volt a ge gener a tor v cc detector timer er as e volt a ge gener a tor inp u t/o u tp u t b u ffer s s ector s witche s chip en ab le o u tp u t en ab le logic y- g a ting cell m a trix addre ss l a tch y-decoder x-decoder d a t a l a tch re s et# ry/by# ( s ee note) a m a x ? a 3 a2?a0 ce# we# dq15?dq0 oe#
12 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 4. connection diagrams/physical dimensions this section contains the i/o designations and package specifications for the opn. 4.1 special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. 4.2 vbh084, 8.0 x 11.6 mm 4.2.1 connection diagram ? s29p l256n mcp compatible package figure 4.1 connection diagram ? 84-ball fine-p itch ball grid array (s29PL256N) notes 1. top view?balls facing down. 2. recommended for wireless applications a7 a3 a2 dq8 dq14 rfu rfu wp#/acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 rfu rst# rfu a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 ry/by# a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 rfu h2 h3 h4 h5 h6 h7 h8 h9 dq10 v cc rfu dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu rfu rfu rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu v cc rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 rfu rfu rfu rfu rfu rfu rfu rfu a1 a10 m1 m10 nc nc nc nc reserved fo r future use legend
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 13 data sheet (preliminary) 4.2.2 physical dimensions ? vbh084, 8.0 x 11.6 mm figure 4.2 physical dimensions ? 84-ball fine-pitch ball grid array (s29PL256N) note recommended for wireless applications 3339 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbh 084 jedec n/a 11.60 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 7.20 bsc. ball footprint md 12 row matrix size d direction me 10 row matrix size e direction n 84 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a2-a9, b10-l10, depopulated solder balls m2-m9, b1-l1) bottom view top view side view a1 corner a2 a 10 9 10 ml j k e c 0.05 (2x) (2x) c 0.05 a1 e d 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 0.10 c c 0.08 nx b sd a b c seating plane a1 corner index mark
14 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 4.3 vbh064, 8 x 11.6 mm 4.3.1 connection diagram ? s29p l127n mcp compatible package figure 4.3 connection diagram ? 64-ball fine-pitch ball grid array (s29pl127n) notes 1. top view?balls facing down. 2. recommended for wireless applications h4 h5 h6 h7 h8 h2 g7 g8 g9 f7 f8 f9 e7 e8 e9 d7 d8 d9 c5 h2 h 2 c6 c7 ce1# h3 oe# rfu dq0 c3 a7 a8 we# wp/acc rfu b5 b7 c8 a11 rfu rfu a15 a12 a19 a21 a13 a9 a22 a14 a10 a16 rfu dq6 e6 rfu a20 g4 f4 e4 e5 d5 rst# rfu ry/by# a18 a17 dq1 rfu dq15 dq13 dq4 dq3 dq9 dq7 rfu v cc dq10 g2 g3 f2 f3 e2 e3 d2 d3 a6 a3 a5 a2 a4 a1 v ss a0 dq8 v ss dq12 dq14 dq5 rfu dq11 dq2 l5 l6 rfu rfu a1 nc a10 nc m10 nc m1 nc h2 c4 d4 d6 reserved for future use no connection j4 j6 j7 j8 j9 j2 j3 k3 k4 k5 k6 k7 k8 legend j5
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 15 data sheet (preliminary) 4.3.2 connection diagram ? s29p l129n mcp compatible package figure 4.4 connection diagram ? 64-ball fine-pitch ball grid array (s29pl129n) notes 1. top view?balls facing down. 2. recommended for wireless applications h4 h5 h6 h7 h8 h2 g7 g8 g9 f7 f8 f9 e7 e8 e9 d7 d8 d9 c5 h2 h 2 c6 c7 ce1# h3 oe# rfu dq0 c3 a7 a8 we# wp/acc rfu b5 b7 c8 a11 rfu rfu a15 a12 a19 a21 a13 a9 ce2# a14 a10 a16 rfu dq6 e6 rfu a20 g4 f4 e4 e5 d5 rst# rfu ry/by# a18 a17 dq1 rfu dq15 dq13 dq4 dq3 dq9 dq7 rfu v cc dq10 g2 g3 f2 f3 e2 e3 d2 d3 a6 a3 a5 a2 a4 a1 v ss a0 dq8 v ss dq12 dq14 dq5 rfu dq11 dq2 l5 l6 rfu rfu a1 nc a10 nc m10 nc m1 nc h2 c4 d4 d6 reserved for future use no connection j4 j6 j7 j8 j9 j2 j3 k3 k4 k5 k6 k7 k8 legend j5
16 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 4.3.3 physical dimensions ? vbh064, 8 x 11.6 mm ? s29pl-n figure 4.5 physical dimensions ? 64-ball fine-pitch ball grid array (s29pl-n) note recommended for wireless applications 3330 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbh 064 jedec n/a 11.60 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 7.20 bsc. ball footprint md 12 row matrix size d direction me 10 row matrix size e direction n 64 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a2-9,b1-4,b7-10,c1-k1, depopulated solder balls m2-9,c10-k10,l1-4,l7-10, g5-6,f5-6) bottom view top view side view a1 corner a2 a 10 9 10 ml j k e c 0.05 (2x) (2x) c 0.05 a1 e d 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 0.10 c c 0.08 nx b sd a b c seating plane a1 corner index mark
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 17 data sheet (preliminary) 5. additional resources visit www.spansion.com to obtain the following related documents: 5.1 application notes ? using the operation status bits in spansion devices ? simultaneous read/write vs. erase suspend/resume ? mirrorbit? flash memory write buffer programming and page buffer read ? design-in scalable wireless solutions with spansion products ? common flash interface version 1.4 vendor specific extensions 5.2 specification bulletins contact your local sales office for details. drivers and software support ? spansion low-level drivers ? enhanced flash drivers ? flash file system cad modeling support ? vhdl and verilog ? ibis ? orcad 5.3 technical support contact your local sales office or contact spansion inc. directly for additional technical support: email us and canada: hw.support@amd.com asia pacific: asia.support@amd.com europe, middle east, and africa japan: http://edevice.fujit su.com/jp/support/tech/#b7 frequently asked questions (faq) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 phone us: (408) 749-5703 japan (03) 5322-3324 spansion inc. locations 915 deguigne drive, p.o. box 3453 sunnyvale, ca 94088-3453, usa telephone: 408-962-2500 or 1-866-spansion spansion japan limited 4-33-4 nishi shinjuku, shinjuku-ku tokyo, 160-0023 telephone: +81-3-5302-2200 facsimile: +81-3-5302-2674 http://www.spansion.com
18 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 6. product overview the s29pl-n family consists of 256 and 128 mb, 3. 0 volts-only, simultaneous read/write page-mode read flash devices that are optim ized for wireless designs of today that demand large storage array and rich functionality, while requiring low power consumpti on. these products also offer 32-word buffer for programming with program and erase suspend/resu me functionality. additional features include: ? advanced sector protection methods for protecting an individual or group of sectors as required, ? 256-word of secured silicon area for stori ng customer and factory secured information ? simultaneous read/write operation 6.1 memory map the s29pl-n devices consist of 4 banks organized as shown in table 6.1 , 6.2 , and 6.3 . note ellipses indicate that other addresses in sector range follow the same pattern. table 6.1 pl256n sector and memory address map bank bank size sector count sector size (kb) sector/ sector range address range notes a 4mb 4 64 sa00 000000h-007fffh sector starting address ? sector ending address 64 sa01 008000h-00ffffh 64 sa02 010000h-017fffh 64 sa03 018000h-01ffffh 15 256 sa04 020000h-03ffffh sector starting address - sector ending address (see note) ? ? ? 256 sa018 1e0000h-1fffffh b 12 mb 48 256 sa19 200000h-21ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa66 7e0000h-7fffffh c 12 mb 48 256 sa67 800000h-81ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa114 de0000h-dfffffh d 4mb 15 256 sa115 e00000h-e1ffffh sector starting address - sector ending address (see note) ? ? ? 256 sa129 fc0000h-fdffffh 4 64 sa130 fe0000h-fe7fffh sector starting address - sector ending address 64 sa131 fe8000h-feffffh 64 sa132 ff0000h-ff7fffh 64 sa133 ff8000h-ffffffh
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 19 data sheet (preliminary) note ellipses indicate that other addresses in sector range follow the same pattern. table 6.2 pl127n sector and memory address map bank bank size sector count sector size (kb) sector/ sector range address range notes a 2 mb 4 64 sa00 000000h-007fffh sector starting address - sector ending address 64 sa01 008000h-00ffffh 64 sa02 010000h-017fffh 64 sa03 018000h-01ffffh 7 256 sa04 020000h-03ffffh sector starting address ? sector ending address (see note) ? ? ? 256 sa10 0e0000h-0fffffh b 6 mb 24 256 sa11 100000h-11ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa34 3e0000h-3fffffh c 6 mb 24 256 sa35 400000h-41ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa58 6e0000h-6fffffh d 2 mb 7 256 sa59 700000h-71ffffh sector starting address - sector ending address (see note) ? ? ? 256 sa65 7c0000h-7dffffh 4 64 sa66 7e0000h-7e7fffh sector starting address - sector ending address 64 sa67 7e80000h-7effffh 64 sa68 7f0000h-7f7fffh 64 sa69 7f8000h-7fffffh table 6.3 pl129n sector and memory address map bank bank size sector count sector size (kb) ce1# ce2# sector/ sector range address range notes 1a 2 mb 4 64 v il v ih sa00 000000h-007fffh sector starting address - sector ending address 64 sa01 008000h-00ffffh 64 sa02 010000h-017fffh 64 sa03 018000h-01ffffh 7 256 sa04 020000h-03ffffh sector starting address ? sector ending address (see note) ? ? ? 256 sa10 0e0000h-0fffffh 1b 6 mb 24 256 sa11 100000h-11ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa34 3e0000h-3fffffh 2a 6 mb 24 256 v ih v il sa35 000000h-01ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa58 2e0000h - 2fffffh 2b 2 mb 7 256 sa59 300000h-31ffffh sector starting address - sector ending address (see note) ? ? ? 256 sa65 3c0000h-3dffffh 4 64 sa66 3e0000h-3e7fffh sector starting address - sector ending address 64 sa67 3e8000h-3effffh 64 sa68 3f0000h-3f7fffh 64 sa69 3f8000h-3fffffh
20 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 7. device operations this section describes the read, program, erase, simu ltaneous read/write operatio ns, and reset features of the flash devices. operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see table 12.1 on page 66 and table 12.2 on page 68 ). the command register itself does not occupy any addre ssable memory location. instead, th e command register is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. writing incorrect address and data values or writing them in an improper sequence can place the device in an unknown st ate, in which case the system must write the reset command to return the device to the reading array data mode. 7.1 device operation table the device must be setup appro priately for each operation. table 7.1 describes the required state of each control pin for any particular operation. legend l = logic low = v il h = logic high = v ih v hh = 8.5 ? 9.5 v x = don?t care sa = sector address a in = address in d in = data in d out = data out note wp#/acc must be high when writing to upper two and lower two sectors (pl256n: 0, 1,132, and 133; pl127/129n: 0, 1, 68, and 69) table 7.1 device operation operation ce# oe# we# reset# wp#/acc addresses (a max ? a0) dq15 ? dq0 read l l h h x a in d out write l h l h x (see note) a in d in standby h x x h x a in high-z output disable l h h h x a in high-z reset x x x l x a in high-z
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 21 data sheet (preliminary) 7.1.1 dual chip enable device descr iption and operation (pl129n only) the dual ce# product (pl129n) offers a reduced number of address pins to accommodate processors with a limited addressable range. this product operates as two separate devices in a single package and requires the processor to address half of the memory space with one chip enable and the remaining memory space with a second chip enable. for more details on the addressing features of the dual ce# device refer to table 6.3 on page 19 for the pl129n sector and memory address map. dual chip enable products must be setup appropriately fo r each operation. to place the device into the active state either ce1# or ce2# must be set to v il . to place the device in standby mode, both ce1# and ce2# must be set to v ih . table 7.2 describes the required state of each control pin for any particular operation. legend l = logic low = v il h = logic high = v ih vid = 11.5?12.5 v v hh = 8.5?9.5v x = don?t care sa = sector address a in = address in d in = data in d out = data out notes 1. the sector and sector unprotect functions may also be implemented by programming equipment. 2. wp#/acc must be high when writing to the upper two and lower two sectors. 7.2 asynchronous read the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory cont ent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. 7.2.1 non-page random read address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable ce# to valid data at the output inputs. the output enable access time is the delay from the falling edge of the oe# to valid dat a at the output (assuming the addresses have been stable for at least t acc ?t oe time). table 7.2 dual chip enable device operation operation ce1# ce2# oe# we# reset# wp#/acc addresses (a21?a0) dq15?dq0 read lh lh h x a in d out hl write lh hl h x (note 2) a in d in hl standby h h x x h x x high-z output disable l l h h h x x high-z reset x x x x l x x high-z temporary sector unprotect (high voltage) x xxx v id xa in d in
22 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 7.2.2 page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access s peed for random locations within a page. the random or initial page access is t acc or t ce and subsequent page read accesses (as l ong as the locations specified by the microprocessor falls within that page) is equivalent to t pac c . when ce# is deasserted (= v ih ), the reassertion of ce# for subsequent access has access time of t acc or t ce . here again, ce# selects the device and oe# is the output control and should be used to ga te data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping a max ? a3 constant and changing a2 ? a0 to select the specific word within that page. address bits a max ? a3 select an 8-word page, and address bits a2 ? a0 select a specif ic word within that page. this is an asynchronous operation with the micr oprocessor supplying the specific word location. see table 7.3 for details on selecting specific words. the device is automatically set to reading array data af ter device power-up. no commands are required to retrieve data. each bank is ready to read array da ta after completing an embedded program or embedded erase algorithm. all addresses are latched on the fallin g edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. reads from the memory array may be performed in conjunction with the erase suspend and program suspend features. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after whic h the system can read data from any non-erase-suspended sector within the same bank. the system can read array data us ing the standard read timing, except that if it reads at an address within erase-suspended sectors, th e device outputs status data. after completing a programming operation in the erase suspend mode, th e system may once again read array data with the same exception. after the device accepts a program suspend command, the corresponding bank enters the program-suspend-read mode, after which the system ca n read data from any non-program-suspended sector within the same bank. table 7.3 word selection within a page word a2 a1 a0 word 0 000 word 1 001 word 2 010 word 3 011 word 4 100 word 5 101 word 6 110 word 7 111
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 23 data sheet (preliminary) 7.3 autoselect the autoselect mode allows the host system to access manufacturer and device identification, and verify sector protection, through identifier code s output from the internal register (separate from the memory array) on dq15-dq0. this mode is primarily intended to allow equipment to automatically match a device to be programmed with its corresponding programming algori thm. when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 7.5) . the remaining address bits are don't care. when all necessary bits have been set as required, the programming equipment can then read the corresponding identifier code on dq15-dq0. the autoselect codes can also be accessed in-system through the command register. note that if a bank address (ba) on the four uppermost address bits is asserted during th e third write cycle of the autoselect command, the host system can read autoselect data fr om that bank and then immediately read array data from the other bank, without exiting the autoselect mode. ? to access the autoselect codes, the host system must issue the autoselect command. ? the autoselect command sequence can be written to an a ddress within a bank that is either in the read or erase-suspend-read mode. ? the autoselect command cannot be written while the devi ce is actively programming or erasing in the other bank. ? autoselect does not support simultaneous operations or page modes. ? the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). see table 12.1 on page 66 for command sequence details. legend l = logic low = v il h = logic high = v ih ba = bank address sa = sector address x = don?t care note for the pl129n either ce1# or ce2# must be low to access autoselect codes table 7.4 autoselect codes description ce# (see note) oe# we# a max ?a12 a10 a9 a8 a7 a6 a5 ?a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id l l h ba x x x l l x l l l l 0001h device id: read cycle 1 l lh ba xxxll l lllh227eh read cycle 2 l h h h l 223ch (pl256n) 2220h (pl127n) 2221h (pl129n) read cycle 3 l h h h h 2200h (pl256n) 2200h (pl127n) 2200h (pl129n) sector protection verification llhsaxxxlllllhl 0000h unprotected (neither dyb nor ppb locked) 0001h protected (either dyb or ppb locked) indicator bit l l h ba x x x l l l l l h h dq15 - dq8 = 0 dq7 - factory lock bit 1 = locked 0 = not locked dq6 -customer lock bit 1 = locked 0 = not locked dq5 - handshake bit 1 = reserved 0 = standard handshake dq4 & dq3 -wp# protection boot code 00 = wp# protects both top boot and bottom boot sectors 11 = no wp# protection dq2 - dq0 = 0
24 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) software functions and sample code notes 1. any offset within the device works. 2. ba = bank address. the bank address is required. 3. base = base address. the following is a c source code example of using the aut oselect function to read the manufacturer id. see the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *((uint16 *)bank_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)bank_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)bank_addr + 0x555) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *((uint16 *)bank_addr + 0x000); /* read manuf. id */ /* autoselect exit */ *((uint16 *)base_addr + 0x000) = 0x00f0; /* exit autoselect (write reset command) */ table 7.5 autoselect entry (lld function = lld_autoselectentrycmd) cycle operation word address data unlock cycle 1 write bax555h 0x00aah unlock cycle 2 write bax2aah 0x0055h autoselect command write bax555h 0x0090h table 7.6 autoselect exit (lld function = lld_autoselectexitcmd) cycle operation word address data unlock cycle 1 write base + xxxh 0x00f0h
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 25 data sheet (preliminary) 7.4 program/erase operations these devices are capable of single word or write bu ffer programming operations which are described in the following sections. the write buffer programming is re commended over single word programming as it has clear benefits from greater programming efficiency. see table 7.1 on page 20 for the correct device settings required before initiation of a write command sequence. note the following details regarding the program/erase operations: ? when the embedded program algorithm is complete, the device then returns to the read mode. ? the system can determine the status of the pr ogram operation by using dq7 or dq6. see write operation status on page 37 for information on these status bits. ? a 0 cannot be programmed back to a 1 . attempting to do so causes the device to set dq5 = 1 (halting any further operation and requiring a reset command). a succeeding read shows that the data is still 0 . ? only erase operations can convert a 0 to a 1 . ? a hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? any commands written to the device during the embedded program algorithm are ignored except the program suspend command. ? secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. ? programming is allowed in any sequence and across sector boundaries for single word programming operation. 7.4.1 single word programming in single word programming mode, four flash command write cycles are used to program an individual flash address. while this method is supported by all span sion devices, in general it is not recommended for devices that support write buffer programming. see table 12.1 on page 66 for the required bus cycles and figure 7.1 on page 26 for the flowchart. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the prog ram operation by using dq7 or dq6. see write operation status on page 37 for information on these status bits. single word programming is supported for backward compat ibility with existing flash driver software and use of write buffer programming is strongly recomm ended for general programming. the effective word programming time using write buffer programming is a pproximately four times faster than the single word programming time.
26 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) figure 7.1 single word program operation software functions and sample code note base = base address. the following is a c source code example of using the single word program function. see the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: program command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x00a0; /* write program setup command */ *((uint16 *)pa) = data; /* write data to be programmed */ /* poll for program completion */ table 7.7 single word program (lld function = lld_programcmd) cycle operation word address data unlock cycle 1 write base + 555h 00aah unlock cycle 2 write base + 2aah 0055h program setup write base + 555h 00a0h program write word address data word write unlock cycle s : addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h write progr a m comm a nd: addre ss 555h, d a t a a0h progr a m d a t a to addre ss : pa , p d unlock cycle 1 unlock cycle 2 s et u p comm a nd progr a m addre ss (pa), progr a m d a t a (pd) fail. i ssu e re s et comm a nd to ret u rn to re a d a rr a y mode. perform polling algorithm ( s ee write oper a tion s t a t us flowch a rt) ye s ye s no no polling s t a t us = b us y? polling s t a t us = done? error condition (exceeded timing limit s ) pa ss . device i s in re a d mode.
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 27 data sheet (preliminary) 7.4.2 write buffer programming write buffer programming allows the system to write a maximum of 32 wo rds in one programming operation. this results in a faster effective wo rd programming time than the standard word programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer lo ad command written at the sector address in which programming occurs. at this point , the system writes the number of word locations minus 1 that is loaded into the page buffer at the sector address in which prog ramming occurs. this tells the device how many write buffer addresses are loaded with data and therefore when to expect the program buffer to flash confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. (number loaded = the number of locations to program minus 1. for example, if the system programs 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starti ng address is the first address/data pair to be programmed, and selects the write-buffer-page address. all subsequent address/data pairs must fall within the elect ed-write-buffer-page. the write-buffer-page is selected by using the addresses a max ?a5. the write-buffer-page addresses must be the same for all addr ess/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer-page . this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer-page , the operation aborts .) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. note that if a write buffer address lo cation is loaded multiple times, the address/data pair counter decrements for every data load operation. also, the last data loaded at a location before the program buffer to flash confirm command is programmed into the device. th e software takes care of the ramifications of loading a write-buffer location more than once. the counte r decrements for each data load operation, not for each unique write-buffer-address loca tion. once the specified number of write buffer locations have been loaded, the system must then write the program buffer to flash command at the sector address. any other address/data write combinations abort the write buffer programming operation. the device then goes busy. the data bar polling techniques should be used while monitoring the last address location loaded into the write buffer. this eliminates the need to store an addr ess in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. the write-buffer embedded programming operation can be suspende d using the standard suspend/resume commands. upon successful completion of the write buff er programming operation, the device returns to read mode. if the write buffer command sequence is entered incorrec tly the device enters write buffer abort. when an abort occurs the write-to buffer-abort reset command must be issued to return the device to read mode. the write buffer programming sequence is aborted under any of the following conditions: ? load a value that is greater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different writ e-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. use of the write buffer is strongly recommende d for programming when multiple words are to be programmed. write buffer programming is approximately four times faster than programming one word at a time. note that the secured silicon, the cfi functions, and the autoselect codes are not available for read when a write buffer programming operation is in progress.
28 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) software functions and sample code notes 1. base = base address. 2. last = last cycle of write buffer program operation; depending on number of words written, the total number of cycles can be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible . the following is a c source code example of us ing the write buffer progr am function. see the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)sector_address) = 0x0025; /* write write buffer load command */ *((uint16 *)sector_address) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *((uint16 *)sector_address) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *((uint16 *)addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)addr + 0x555) = 0x00f0; /* write buffer abort reset */ table 7.8 write buffer program (lld functions used = lld_writetobuf fercmd, lld_programbuffertoflashcmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 write buffer load command write program address 0025h 4 write word count write program address word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 29 data sheet (preliminary) figure 7.2 write buffer programming operation write unlock cycle s : addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h i ssu e write b u ffer lo a d comm a nd: addre ss 555h, d a t a 25h lo a d word co u nt to progr a m progr a m d a t a to addre ss : s a = wc unlock cycle 1 unlock cycle 2 wc = n u m b er of word s ? 1 ye s ye s ye s ye s ye s no no no no no wc = 0? write b u ffer a b ort de s ired? write b u ffer a b ort? polling s t a t us = done? error? fail. i ssu e re s et comm a nd to ret u rn to re a d a rr a y mode. write to a different s ector addre ss to c aus e write b u ffer a b ort pa ss . device i s in re a d mode. confirm comm a nd: s a 29h w a it 4 s perform polling algorithm ( s ee write oper a tion s t a t us flowch a rt) write next word, decrement wc: pa d a t a , wc = wc ? 1 re s et. i ssu e write b u ffer a b ort re s et comm a nd
30 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 7.4.3 sector erase the sector erase function erases one or mo re sectors in the memory array. (see table 12.1 on page 66 , and figure 7.3 on page 31 .) the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies th e entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea occurs. during the time- out period, additional sector addresses and sector erase commands can be written. loading the sector erase buffer can be done in any sequence, and the number of sectors can be from one sector to all sectors. the time between these additional cycles must be less than t sea . any sector erase address and command following the exceeded time-out (t sea ) may or may not be accepted. any command other than sector erase or erase suspend during the time-out period resets th at bank to the read mode. t he system can monitor dq3 to determine if the sector erase timer has timed out (see dq3: sector erase timeout state indicator on page 40 ). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing banks. the system can determine t he status of the erase ope ration by reading dq7 or dq6/dq2 in the erasing bank. see write operation status on page 37 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset imme diately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 7.3 on page 31 illustrates the algorithm for the erase operation. see ac characteristics on page 59 for the erase/program operations parameters and timing diagrams. software functions and sample code note unlimited additional sectors can be selected for erase; command(s) must be written within t sea . the following is a c source code example of us ing the sector erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0080; /* write setup command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write additional unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write additional unlock cycle 2 */ *((uint16 *)sector_address) = 0x0030; /* write sector erase command */ table 7.9 sector erase (lld function = lld_sectorerasecmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 setup command write base + 555h 0080h 4 unlock write base + 555h 00aah 5 unlock write base + 2aah 0055h 6 sector erase command write sector address 0030h
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 31 data sheet (preliminary) figure 7.3 sector erase operation notes 1. see table 12.1 on page 66 for erase command sequence. 2. see the section on dq3 for information on the sector erase timeout. no write s ector er as e cycle s : addre ss 555h, d a t a 8 0h addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h s ector addre ss , d a t a 3 0h write addition a l s ector addre ss e s fail. write re s et comm a nd to ret u rn to re a ding a rr a y. pa ss . device ret u rn s to re a ding a rr a y. w a it 4 s perform write oper a tion s t a t us algorithm s elect addition a l s ector s ? ye s ye s ye s ye s ye s no no no no l as t s ector s elected? done? dq5 = 1? comm a nd cycle 1 comm a nd cycle 2 comm a nd cycle 3 s pecify fir s t s ector for er asu re error condition (exceeded timing limit s ) s t a t us m a y b e o b t a ined b y re a ding dq7, dq6 a nd/or dq2. poll dq 3 . dq 3 = 1? ? e a ch a ddition a l cycle m us t b e written within t s ea timeo u t ? timeo u t re s et s a fter e a ch a ddition a l cycle i s written ? the ho s t s y s tem m a y monitor dq 3 or w a it t s ea to en su re a ccept a nce of er as e comm a nd s ? no limit on n u m b er of s ector s ? comm a nd s other th a n er as e sus pend or s electing a ddition a l s ector s for er asu re d u ring timeo u t re s et device to re a ding a rr a y d a t a
32 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 7.4.4 chip erase command sequence chip erase is a six-bus cycle operation as indicated by table 12.1 on page 66 . these commands invoke the embedded erase algorithm, which does not require the system to preprog ram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definition tables ( table 12.1 on page 66 and table 12.2 on page 68 ) show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by us ing dq7 or dq6/dq2. see write operation status on page 37 for information on these status bits. any commands written during the chip erase operati on are ignored. however, note that a hardware reset immediately terminates the erase operation. if that o ccurs, the chip erase command sequence should be reinitiated once that bank has returned to read ing array data, to ens ure data integrity. software functions and sample code the following is a c source code example of us ing the chip erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0080; /* write setup command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write additional unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write additional unlock cycle 2 */ *((uint16 *)base_addr + 0x000) = 0x0010; /* write chip erase command */ table 7.10 chip erase (lld function = lld_chiperasecmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 setup command write base + 555h 0080h 4 unlock write base + 555h 00aah 5 unlock write base + 2aah 0055h 6 chip erase command write base + 555h 0010h
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 33 data sheet (preliminary) 7.4.5 erase suspend/erase resume commands the erase suspend command allows the system to inte rrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the minimum t sea time-out period during the sector er ase command sequence. the erase suspend command is ignored if written during the chip erase operation. when the erase suspend command is written during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation. however, when the erase suspend command is written during the sector erase ti me-out, the device immediately terminates the time- out period and suspends the erase operation. after the erase operation has been suspended, the ba nk enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) reading at any addre ss within erase-suspended se ctors produces status information on dq7-dq0. th e system can use dq7, or dq6, and dq2 t ogether, to determine if a sector is actively erasing or is erase-suspended. refer to table 7.18 on page 40 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq 7 or dq6 status bits, just as in the standard program operation. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. see write buffer programming on page 27 and autoselect on page 23 for details. to resume the sector erase operation, the syst em must write the erase resume command. the bank address of the erase-suspended bank is required when wr iting this command. furthe r writes of the resume command are ignored. another erase su spend command can be written afte r the chip has resumed erasing. software functions and sample code the following is a c source code example of us ing the erase suspend function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: erase suspend command */ *((uint16 *)bank_addr + 0x000) = 0x00b0; /* write suspend command */ the following is a c source code example of us ing the erase resume function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: erase resume command */ *((uint16 *)bank_addr + 0x000) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ table 7.11 erase suspend (lld function = lld_erasesuspendcmd) cycle operation word address data 1 write bank address 00b0h table 7.12 erase resume (lld function = lld_eraseresumecmd) cycle operation word address data 1 write bank address 0030h
34 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 7.4.6 program suspend/p rogram resume commands the program suspend command allows the system to interrupt an embedded programming operation or a write to buffer programming operation so that data can read from any non-suspended sector. when the program suspend command is written during a progra mming process, the device halts the programming operation within t psl (program suspend latency) and updates the status bits. after the programming operation has been suspended, the system can read array data from any non- suspended sector. the program suspend command can also be issued during a programming operation while an erase is suspended. in this case, data can be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then us er must use the proper command sequences to enter and exit this region. the system can also write the autoselect command se quence when the device is in program suspend mode. the device allows reading autoselect codes in the sus pended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to program suspend mode, and is ready for another valid operation. see autoselect on page 23 for more information. after the program resume command is written, th e device reverts to prog ramming. the system can determine the status of the program operation using the dq7 or dq6 stat us bits, just as in the standard program operation. see write operation status on page 37 for more information. the system must write the program resume command (address bits are don't cares ) to exit the program suspend mode and continue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resumed programming. software functions and sample code the following is a c source code example of usin g the program suspend function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: program suspend command */ *((uint16 *)base_addr + 0x000) = 0x00b0; /* write suspend command */ the following is a c source code example of usi ng the program resume function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: program resume command */ *((uint16 *)base_addr + 0x000) = 0x0030; /* write resume command */ table 7.13 program suspend (lld function = lld_programsuspendcmd) cycle operation word address data 1 write bank address 00b0h table 7.14 program resume (lld function = lld_programresumecmd) cycle operation word address data 1 write bank address 0030h
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 35 data sheet (preliminary) 7.4.7 accelerated program accelerated single word pr ogramming, write buffer programming, sector erase, and chip erase operations are enabled through the acc function. this method is fa ster than the standard chip program and erase command sequences. the accelerated ch ip program and erase functions must not be used more than 10 times per sector. in addition, accelerated chip program and er ase should be performed at room temperature (25 c 10 c). this function is primarily intended to allow faster manufacturing throughput at t he factory. if the system asserts v hh on this input, the device automatically enters the aforementioned unlock bypass mode and uses the higher voltage on the input to reduce the time re quired for program and erase operations. the system can then use the write buffer load command sequence prov ided by the unlock bypass mode. note that if a write-to-buffer-abort reset is required while in unlock bypass mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded program or erase operation, returns the device to normal operation. ? sectors must be unlocked prior to raising wp#/acc to v hh . ? the wp#/acc must not be at v hh for operations other than accelerated programming and accelerated chip erase, or device damage can result. ? set the acc pin at v cc when accelerated programming not in use. 7.4.8 unlock bypass the device features an unlock bypass mode to facilitate faster word programming. once the device enters the unlock bypass mode, only two write cycles are r equired to program data, in stead of the normal four cycles. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 12.1, memory array commands on page 66 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode , the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contai n the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode.
36 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) software functions and sample code the following are c source code examples of using t he unlock bypass entry, program, and exit functions. refer to the spansion low level driver user?s guide (available soon on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: unlock bypass entry command */ *((uint16 *)bank_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)bank_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)bank_addr + 0x555) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *((uint16 *)bank_addr + 0x555) = 0x00a0; /* write program setup command */ *((uint16 *)pa) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; table 7.15 unlock bypass entry (lld function = lld_unlockbypassentrycmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 entry command write base + 555h 0020h table 7.16 unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation word address data 1 program setup command write base +xxxh 00a0h 2 program command write program address program data table 7.17 unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation word address data 1 reset cycle 1 write base +xxxh 0090h 2 reset cycle 2 write base +xxxh 0000h
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 37 data sheet (preliminary) 7.4.9 write oper ation status the device provides several bits to determine the st atus of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling. the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the co mmand sequence. note that the data# polling is valid only for the last word being programmed in the writ e-buffer-page during write buffer programming. reading data# polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately t psp , then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read m ode. if not all selected sectors are protected, the embedded eras e algorithm erases the unpr otected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address withi n a protected sector, the status may not be valid. just prior to the completion of an embedded progra m or erase operation, dq7 can change asynchronously with dq6 ? dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6 ? dq0 may be still invalid. valid data on dq7 ? dq0 appears on successive read cycles. see the following for more information: table 7.18, write operation status on page 40 , shows the outputs for data# polling on dq7. figure 7.4, write operation status flowchart on page 38 , shows the data# polling algorithm. figure 11.13, data# polling timings (during embedded algorithms) on page 64 shows the data# polling timing diagram.
38 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) figure 7.4 write operation status flowchart notes 1. dq6 is toggling if read2 dq6 does not equal read3 dq6. 2. dq2 is toggling if read2 dq2 does not equal read3 dq2. 3. may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4. write buffer error if dq1 of last read =1. 5. invalid state, use reset command to exit operation. 6. valid data is the data that is intended to be programmed or all 1's for an erase operation. 7. data polling algorithm valid for all operations except advanced sector protection. start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5)
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 39 data sheet (preliminary) dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i can be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and du ring the sector erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately t asp (all sectors protected toggle time), then return s to reading array data . if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7, see dq7: data# polling. on page 37 if a program address falls within a protec ted sector, dq6 toggles for approximately t pa p after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: figure 7.4, write operation status flowchart on page 38 , figure 11.14, toggle bit timings (during embedded algorithms) on page 64 , table 7.18, write operation status on page 40 , and figure 11.15, dq2 vs. dq6 on page 64 . toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state. dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 7.18 on page 40 to compare outputs for dq2 and dq6. see the following for additional information: figure 7.4, write operation status flowchart on page 38 and figure 11.14, toggle bit timings (during embedded algorithms) on page 64 . reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit st atus, it must read dq7 ? dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, th e system would note and store the value of the toggle bit after the first read. after the second read, th e system would compare the new value of the toggle bit with the first. if the toggle bit is no t toggling, the device has completed the program or erases operation. the system can read array data on dq7 ? dq0 on the following read cycle. howeve r, if after the initial two read cycles, the system determines that the toggle bit is st ill toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit might have st opped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully comple ted the program or erases operation. if it is still toggling, the device did not complete the operati on successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. th e system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it can choose to perform other system tasks. in this ca se, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to figure 7.4, write operation status flowchart on page 38 for more details.
40 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that th e program or erase cycle was not successfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1 , under this condition, the device halts the operation, and when the ti ming limit has been exceeded, dq5 produces a 1 . under both these conditions, the system must write the reset comm and to return to the read mode (or to the erase- suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timeout state indicator after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure has begun. (the sector erase ti mer does not apply to the chip eras e command.) if additional sectors are selected for erasure, the entire time-out also ap plies after each additional sector erase command. when the time-out period is comp lete, dq3 switches from a 0 to a 1 . if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see sector erase command sequence for more details. after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts additional sector erase commands. to ensure the command has been accepted, the system softwa re should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq 3 is high on the second status check, the last command might not have been accepted. table 7.18 shows the status of dq3 relative to the other status bits. dq1: write to buffer abort dq1 indicates whether a write to buffer operation wa s aborted. under these conditions dq1 produces a 1 . the system must issue the write to buffer abort rese t command sequence to return the device to reading array data. see write buffer program ming operation for more details. notes 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer programming operations. note that dq7# during write buffer pro gramming indicates the data-bar for dq7 data for the last loaded write-buffer address location. 7.5 simultaneous read/write the simultaneous read/write f eature allows the host system to read da ta from one bank of memory while programming or erasing another bank of memory. an er ase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). figure 11.12, back-to-back read/write cycle timings on page 63 shows how read and write cycles may be initiated for simultaneous table 7.18 write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) program suspend mode (note 3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data data data data data data erase-suspend-program dq7# toggle 0 n/a n/a n/a write to buffer (note 5) busy state dq7# toggle 0 n/a n/a 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 abort state dq7# toggle 0 n/a n/a 1
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 41 data sheet (preliminary) operation with zero latency. see the table, dc characteristics on page 57 for read-while-program and read- while-erase current specifications. figure 7.5 simultaneous operation block diagram for s29PL256N and s29pl127n note a max = a23 (pl256n), a22 (pl127n) v cc v ss b a nk a addre ss b a nk b addre ss a m a x ? a0 re s et# we# ce# dq0 ? dq15 s t a te control a nd comm a nd regi s ter ry/by# b a nk a x-decoder oe# dq15 ? dq0 s t a t us control a m a x ?a0 a m a x ? a0 a m a x ? a0 a m a x ?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 m u x m u x m u x b a nk b x-decoder y- g a te b a nk c x-decoder b a nk d x-decoder y- g a te b a nk c addre ss b a nk d addre ss wp#/acc
42 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) figure 7.6 simultaneous operation block diagram for s29pl129n 7.6 writing commands/command sequences during a write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an er ase operation can erase one sector, multiple sectors, or the entire device. table 6.1 on page 18 and table 6.2 on page 19 indicate the address space that each sector occupies. the device address space is divided into four banks: banks b and c contain only 128 kword sectors, while banks a and d contain both 32 kword boot sectors in addition to 128 kword sectors. a bank address is the set of address bits required to uniquely select a bank. similarly, a sector address is the address bits required to uniquely select a sector. i cc2 in dc characteristics on page 57 represents the active current specification fo r the write mode. see ac characteristics on page 59 contains timing specification tables and timing diagrams for write operations. 7.7 hardware reset the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, and ignores all read/write commands for th e duration of the reset# pulse. the device also resets the internal state machine to reading array data. to ensure data integrity the operation that was interrupted should be rein itiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. reset# may be tied to the system reset circuitry whic h enables the system to read the boot-up firmware from the flash memory upon a system reset. see figure 11.5 on page 56 and figure 11.8 on page 60 for timing diagrams. v cc v ss b a nk 1a addre ss b a nk 1b addre ss a21 ? a0 re s et# we# ce1# dq0 ? dq15 ce2# s t a te control a nd comm a nd regi s ter ry/by# b a nk 1a x-decoder oe# s t a t us control a21 ? a0 a21 ? a0 a21 ? a0 a21 ? a0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 m u x m u x m u x b a nk 1b x-decoder y- g a te b a nk 2a x-decoder b a nk 2b x-decoder y- g a te b a nk 2a addre ss b a nk 2b addre ss ce1# = l ce2# = h ce1# = h ce2# = l wp#/acc
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 43 data sheet (preliminary) 7.8 software reset software reset is part of the command set (see table 12.1 on page 66 ) that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. to reset software when dq5 goes high during writ e status operation that indicates program or erase cycle was not successfully completed 3. to exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if the device was previously in erase suspend mode. 5. to reset software after any aborted operations software functions and sample code note base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on span sion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the banks to t he read and address bits are ignored. ? reset commands are ignored once erasure has begun until the operation is complete. ? once programming begins, the device ignores reset commands until the operation is complete ? the reset command may be written between the cycles in a program command sequence before programming begins (prior to the thir d cycle). this resets the bank to which the system was writing to the read mode. ? if the program command sequence is written to a bank t hat is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. ? if a bank has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? if dq1 goes high during a write buffer progra mming operation, the system must write the write to buffer abort reset command sequence to reset the device to reading array data. the standard reset command does not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence (see command tables for detail). table 7.19 reset (lld function = lld_resetcmd) cycle operation word address data reset command write base + xxxh 00f0h
44 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 8. advanced sector protection/unprotection the advanced sector protec tion/unprotection feature disables or ena bles programming or erase operations in any or all sectors and can be implemented thr ough software and/or hardware methods, which are independent of each other. this sectio n describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 8.1 on page 44 . figure 8.1 advanced sector protection/unprotection hardware methods software methods wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit ( notes 1, 2, 3 ) 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n (note 4) ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppd) ( notes 5, 6 ) dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) (notes 7, 8, 9) notes: 1. bit is volatile, and defaults to 1 on reset. 2. programming to 0 locks all ppbs to their current state. 3. once programmed to 0, requires hardware reset to unlock. 4. n = highest address sector. 5. 0 = sector protected, 1 = sector unprotected. 6. ppbs programmed individually, but cleared collectively. 7. 0 = sector protected, 1 = sector unprotected. 8. protect effective only if ppb lock bit is unlocked and corresponding ppb is 1 (unprotected). 9. volatile bits: defaults to user choice upon power-up (see ordering options).
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 45 data sheet (preliminary) 8.1 lock register as shipped from the factory, all devices default to th e persistent mode when power is applied, and all sectors are unprotected, unless otherwise chos en through the dyb ordering option (see ordering information on page 9 ). the device programmer or host system must then choose which sector protection method to use. programming (setting to 0 ) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: ? lock register persistent protection mode lock bit (dq1) ? lock register password protection mode lock bit (dq2) for programming lock register bits see table 12.2 on page 68 . notes 1. if the password mode is chosen, the pass word must be programmed before setting the corresponding lock register bit. 2. after the lock register bits command set entry command sequence is written, reads and writes for bank a are disabled, while reads from othe r banks are allowed until exiting this mode. 3. if both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 4. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the protection scheme are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. after selecting a sector protection method, each sect or can operate in any of the following three states: 1. constantly locked. the selected sectors are protected and cannot be reprogrammed unless ppb lock bit is cleared via a password, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protect ed and can be altered via software commands. 3. unlocked. the sectors are unprotected and c an be erased and/or programmed. these states are controlled by the bit types described in sections 8.2 ? 8.6 . table 8.1 lock register device dq15 ? 05 dq4 dq3 dq2 dq1 dq0 s29PL256N undefined dyb lock boot bit 0 = sectors power up protected 1 = sectors power up unprotected ppb one-time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit
46 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 8.2 persistent protection bits the persistent protection bits ar e unique and nonvolatile for each sector and have the same endurances as the flash memory. preprogramming and verification prio r to erasure are handled by the device, and therefore do not require system monitoring. notes 1. each ppb is individually programm ed and all are eras ed in parallel. 2. entry command disables reads and writes for the bank selected. 3. reads within that bank return the ppb status for that sector. 4. reads from other banks are allow ed while writes are not allowed. 5. all reads must be performed using the asynchronous mode. 6. the specific sector addresses (a23 ? a14 pl25 6n and a22 ? a14 pl127n/pl129n) are written at the same time as the program command. 7. if the ppb lock bit is set, the ppb program or erase command does not execute and times-out without programming or erasing the ppb. 8. there are no means for individually erasing a s pecific ppb and no specific sector address is required for this operation. 9. exit command must be issued after the executi on which resets the device to read mode and re- enables reads and writes for bank a. 10. the programming state of the ppb for a given sect or can be verified by writing a ppb status read command to the device as described by the flow chart below. 8.3 dynamic protection bits dynamic protection bits are volatile and unique for eac h sector and can be individually modified. dybs only control the protection scheme fo r unprotected sectors that have their ppbs cleared (erased to 1 ). by issuing the dyb set or clear command sequences, the dybs are set (programmed to 0 ) or cleared (erased to 1 ), thus placing each sector in the prot ected or unprotected state respective ly. this feature allows software to easily protect sectors against inadvertent changes ye t does not prevent the easy removal of protection when changes are needed. notes 1. the dybs can be set (programmed to 0 ) or cleared (erased to 1 ) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to 1 ) and upon power up or reset, the dybs can be set or cleared depending upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to 1 ), then the sectors may be modified depending upon the ppb state of that sector. 3. the sectors would be in the protected state if t he option to set the dybs after power up is chosen (programmed to 0 ). 4. it is possible to have sectors that are persistent ly locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dynamic se ctors signify protected or unprotected state of the sectors respectively. however, if there is a ne ed to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit onc e again locks the ppbs, a nd the device operates normally again. 6. to achieve the best prot ection, it is recommended to execute the ppb lock bit set command early in the boot code and protect the boot code by holding wp# = v il . note that the ppb and dyb bits have the same function when wp#/acc = v hh as they do when wp#/acc = v ih .
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 47 data sheet (preliminary) 8.4 persistent protection bit lock bit the persistent protection bit lock bit is a global vo latile bit for all sectors. when set (programmed to 0 ), this bit locks all ppb and when cleared (programmed to 1 ), unlocks each sector. ther e is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set (programmed to 0 ) only after all ppbs are c onfigured to the desired settings. 8.5 password protection method the password protection method allows an even higher leve l of security than the pers istent sector protection mode by requiring a 64-bit password for unlocking the device ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bit is set 0 to maintain the password mode of operation. successful execution of the password unlock command by entering the entire password clears the ppb lock bit, allowing for sector ppbs modifications. notes 1. there is no special addressing order required for programming the password. once the password is written and verified, the password mode locking bit must be set to prevent access. 2. the password program command is only capable of programming 0 s. programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0 . 3. the password is all 1 s when shipped from the factory. 4. all 64-bit password combinations are valid as a password. 5. there is no means to verify what the password is after it is set. 6. the password mode lock bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 7. the password mode lock bit is not erasable. 8. the lower two address bits (a1 ? a0) are valid during the password read, password program, and password unlock. 9. the exact password must be entered in order for the unlocking function to occur. 10. the password unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combin ations in an attempt to correctly match a password. 11. approximately 1 s is required for unlocking the devi ce after the valid 64-bit password is given to the device. 12. password verification is only allowed during the password programming operation. 13. all further commands to the password region are disabled and all operations are ignored. 14. if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock bit. 15. entry command sequence must be issued prior to any of any operation and it disables reads and writes for bank a. reads and writes for other banks excluding bank a are allowed. 16. if the user attempts to program or erase a pr otected sector, the device ignores the command and returns to read mode. 17. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the c ontents of the protected sector. 18. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read commands dyb status, ppb status, and ppb lock status to the device.
48 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) figure 8.2 lock register program algorithm 8.6 advanced sector protection software examples table 8.2 contains all possibl e combinations of the dyb, ppb, and ppb lock bit relating to the status of the sector. in summary, if the ppb lock bit is locked (set to 0 ), no changes to the ppbs are allowed. the ppb lock bit can only be unlocked (reset to 1 ) through a hardware reset or power cycle. see also figure 8.1 on page 44 for an overview of the advanced sector protection feature. write unlock cycle s : addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h write enter lock regi s ter comm a nd: addre ss 555h, d a t a 40h progr a m lock regi s ter d a t a addre ss xxxh, d a t a a0h addre ss 77h*, d a t a pd unlock cycle 1 unlock cycle 2 xxxh = addre ss don?t c a re * not on f u t u re device s progr a m d a t a (pd): s ee text for lock regi s ter definition s c au tion: lock d a t a m a y only b e prog a mmed once. w a it 4 s pa ss . write lock regi s ter exit comm a nd: addre ss xxxh, d a t a 90h addre ss xxxh, d a t a 00h device ret u rn s to re a ding a rr a y. perform polling algorithm ( s ee write oper a tion s t a t us flowch a rt) ye s ye s no no done? dq5 = 1? error condition (exceeded timing limits) fail. write re s t comm a nd to ret u rn to re a ding a rr a y. table 8.2 sector protection schemes unique device ppb lock bit 0 = locked, 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 49 data sheet (preliminary) 8.7 hardware data protection methods the device offers data protection at the sector level via hardware control: ? when wp#/acc is at v il , the four outermost sectors are locked (device specific). there are additional methods by which intended or acci dental erasure of any se ctors can be prevented via hardware means. the following subs ections describes these methods: 8.7.1 wp# method the write protect feature provides a hardware method of protecting the four outermos t sectors. this function is provided by the wp#/acc pin and overrides the previously discussed sector protection/unprotection method. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the outermost boot sectors. the outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protecti on or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp#/acc pin must not be left floating or unconnected as inconsistent behavior of the device may result. the wp#/acc pin must be held stable during a command sequence execution 8.7.2 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase ci rcuits are disabled, and the device resets to reading array data. subsequent wr ites are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . 8.7.3 write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, ce# or we # do not initiate a write cycle. 8.7.4 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device d oes not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on powerup.
50 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 9. power conservation modes 9.1 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in dc characteristics on page 57 represents the standby current specification 9.2 automatic sleep mode the automatic sleep mode minimizes flash device e nergy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# contro l signals. standard address access timings provide new data when addresses are changed. while in sleep mo de, output data is latched and always available to the system. i cc6 in dc characteristics on page 57 represents the automatic slee p mode current specification. 9.3 hardware reset# input operation the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, resets the configuration register, and ig nores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma chine to reading array data. the ope ration that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. reset# may be tied to the system reset circuitry and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. 9.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state.
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 51 data sheet (preliminary) 10. secured silicon sector flash memory region the secured silicon sector provides an extra flash memo ry region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 word s in length that consists of 128 words for factory data and 128 words for custome r-secured areas. all secured silicon reads outside of the 256-word address range returns invalid data. the fact ory indicator bit, dq7, (a t autoselect address 03h) is used to indicate whether or not the factory secured silicon sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secured silicon sector is locked when shipped from the factory. note the following general conditions: ? while the secured silicon sector access is enabled, simultaneous operations are allowed except for bank a. ? on power up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads outside of sector 0 return memory array data. ? sector 0 is remapped from the memory array to the secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible when the device is executing an embedded program or embedded erase algorithm. 10.1 factory secured silicon sector the factory secured silicon sector is always protected when shipped fr om the factory and has the factory indicator bit (dq7) permanently set to a 1 . this prevents cloning of a fa ctory locked part and ensures the security of the esn and customer code once the product is shipped to the field. these devices are available pre pr ogrammed with one of the following: ? a random, 8-word secure esn only within the factory secured silicon sector ? customer code within the customer secu red silicon sector through the spansion tm programming service. ? both a random, secure esn and customer code through the spansion programming service. customers may opt to have their code programmed th rough the spansion programming services. spansion programs the customer's code, with or without t he random esn. the devices are then shipped from the spansion factory with the factory secured silicon sector and customer secured s ilicon sector permanently locked. contact your local representative for details on using spansion programming services. table 10.1 secured silicon sector addresses sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh
52 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 10.2 customer secured silicon sector the customer secured silicon sector is typically shipped unprotected (dq6 set to 0 ), allowing customers to utilize that sector in any manner they choose. if the security feature is not required, the customer secured silicon sector can be treated as an additional flash memory space. please note the following: ? once the customer secured silicon sector area is pr otected, the customer indicator bit is permanently set to 1 . ? the customer secured silicon sector can be read any number of times, but can be programmed and locked only once. the customer secured silicon sector lock must be used with caution as once locked, there is no procedure available for unlocking the cust omer secured silicon sector area and none of the bits in the customer secured silicon sect or memory space can be modified in any way. ? the accelerated programming (acc) and unlock bypass functions are not available when programming the customer secured silicon sector, but are available when reading in banks b through d. ? once the customer secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command sequence which return the device to the memory array at sector 0. 10.3 secured silicon sector en try and exit command sequences the system can access the secured s ilicon sector region by issuing th e three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four-cycle exit secu red silicon sector command sequence. see the command definition tables: table 12.1, memory array commands on page 66 , table 12.2, sector protection commands on page 68 for address and data requirements for both command sequences. the secured silicon sector entry command allows the following commands to be executed ? read customer and factor y secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues unt il the system issues the exit secured silicon sector command sequence, or until power is removed from the device.
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 53 data sheet (preliminary) software functions and sample code the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level driver user guide (available soon on www.spansion.com ) for general information on spansion flash memory software development guidelines. note base = base address. /* example: secsi sector entry command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0088; /* write secsi sector entry cmd */ note base = base address. /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ note base = base address. /* example: secsi sector exit command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0090; /* write secsi sector exit cycle 3 */ *((uint16 *)base_addr + 0x000) = 0x0000; /* write secsi sector exit cycle 4 */ table 10.2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) cycle operation word address data unlock cycle 1 write base + 555h 00aah unlock cycle 2 write base + 2aah 0055h entry cycle write base + 555h 0088h table 10.3 secured silicon sector program (lld function = lld_programcmd) cycle operation word address data unlock cycle 1 write base + 555h 00aah unlock cycle 2 write base + 2aah 0055h program setup write base + 555h 00a0h program write word address data word table 10.4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) cycle operation word address data unlock cycle 1 write base + 555h 00aah unlock cycle 2 write base + 2aah 0055h exit cycle write base + 555h 0090h
54 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 11. electrical specifications 11.1 absolute maximum ratings notes 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 on page 54 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 11.2 on page 54 . 2. minimum dc input voltage on pin wp# ? acc is ?0.5 v. during voltage transitions, wp# ? acc may overshoot v ss to 2.0 v for periods of up to 20 ns. see figure 11.1 on page 54 . maximum dc voltage on pin wp# ? acc is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under absolute maximum ratings on page 54 may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this data sheet is not implied. exposure of the device to absolute maximu m rating conditions for extended periods may affect device relia bility. figure 11.1 maximum negative overshoot waveform figure 11.2 maximum positive overshoot waveform storage temperature, plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) ?0.5 v to v io + 0.5 v v cc (note 1) ?0.5 v to +4.0 v v io (note 1) ?0.5 v to +4.0v acc (note 2) ?0.5 v to +10.5 v output short circuit current (note 3) 200 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 55 data sheet (preliminary) 11.2 operating ranges notes 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. for all ac and dc specifications, v io = v cc . 3. voltage range of 2.7 ? 3.1 v valid for pl-n mcp products. 11.3 test conditions figure 11.3 test setup 11.4 key to switching waveforms wireless (w) devices ?25c to +85c ambient temperature (t a ) industrial (i) devices ?40c to +85c ambient temperature (t a ) v cc supply voltages (note 3) +2.7 v to 3.1 v or +2.7 v to +3.6 v table 11.1 test specifications test condition all speeds unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times v cc = 3.0 v 5 ns input pulse levels v cc = 3.0 v 0.0 ? 3.0 v input timing measurement reference levels v cc /2 v output timing measurement reference levels v cc /2 v c l device under test waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
56 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 11.5 switching waveforms figure 11.4 input waveforms and measurement levels 11.6 v cc power up notes 1. v cc ramp rate must exceed 1 v/400 s. 2. v io is internally connected to v cc . figure 11.5 v cc power-up diagram v io 0.0 v output measurement level input v cc /2 v cc /2 all inputs and outputs parameter description test setup speed unit t vcs v cc setup time min 250 s t read time between reset# high and ce# low min 200 ns v cc reset# t vcs t read ce# v cc min v ih
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 57 data sheet (preliminary) 11.7 dc characteristics 11.7.1 dc characteristics (v cc = 2.7 v to 3.6 v) (cmos compatible) notes 1. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc =v cc max, t a =t a max. typical i cc specifications are with typical v cc =3.0 v, t a = +25c. 3. i cc is active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc +30 ns. typical sleep mode current is 1 a. 5. not 100% tested. 6. the data in the table is for v cc range 2.7 v to 3.6 v (recommended for standalone applications). 7. ce1# and ce2# for the pl129n. parameter symbol parameter description (notes) test conditions min (note 2) typ (note 2) max unit i li input load current v in =v ss to v cc , v cc =v cc max ( 6 )2.0a i lo output leakage current v out =v ss to v cc , oe# = v ih v cc =v cc max ( 6 ) 1.0 a i cc1 v cc active read current ( 1 , 3 ) oe# = v ih , v cc =v cc max ( 1 , 6 ) 5 mhz 30 45 ma i cc2 v cc active write current ( 3 )oe#=v ih , we# = v il 25 50 ma i cc3 v cc standby current ce# ( 7 ), reset#, wp#/acc = v cc 0.3 v 20 40 a i cc4 v cc reset current reset# = v ss 0.3 v 300 500 a i cc5 automatic sleep mode ( 4 )v ih =v cc 0.3 v; v il =v ss 0.3 v 20 40 a i cc6 v cc active read-while-write current ( 1 ) oe# = v ih 5 mhz 35 50 ma i cc7 v cc active program-while-erase- suspended current ( 5 ) oe# = v ih 27 55 ma i cc8 v cc active page read current oe# = v ih , 8 word page read 40 mhz 6 10 ma v il input low voltage v cc = 2.7 to 3.6 v ?0.5 0.8 v v ih input high voltage v cc = 2.7 to 3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% ( 6 )8.59.5v v ol output low voltage i ol = 100 a, v cc =v cc min ( 6 )0.1v v oh output high voltage i oh = ?100 a ( 6 )v cc ?0.2 v v lko low v cc lock-out voltage ( 5 )2.32.5v
58 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 11.7.2 dc characteristics (v cc = 2.7 v to 3.1 v) (cmos compatible) notes 1. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc =v cc max, t a =t a max. typical i cc specifications are with typical v cc =2.9 v, t a = +25c. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 1 a. 5. not 100% tested. 6. data in table is for v cc range 2.7 v to 3.1 v (recommended for mcp applications) 7. ce1# and ce2# for the pl129n. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current v in =v ss to v cc , v cc =v cc max ( 6 )2a i lo output leakage current v out =v ss to v cc , oe# = v ih v cc =v cc max ( 6 ) 1 a i cc1 v cc active read current ( 1 , 2 ) oe# = v ih , v cc =v cc max ( 1 , 6 ) 5mhz 28 40 ma i cc2 v cc active write current ( 2 , 3 )oe#=v ih , we# = v il 22 40 ma i cc3 v cc standby current ( 2 ) ce# ( 7 ), reset#, wp#/acc =v cc 0.3 v 20 40 a i cc4 v cc reset current ( 2 ) reset# = v ss 0.3 v 300 500 a i cc5 automatic sleep mode ( 2 , 4 )v ih =v cc 0.3 v; v il =v ss 0.1 v 20 40 a i cc6 v cc active read-while-write current ( 1 , 2 ) oe# = v ih 5mhz 33 45 ma i cc7 v cc active program-while-erase- suspended current ( 2 , 5 ) oe# = v ih 24 45 ma i cc8 v cc active page read current ( 2 ) oe# = v ih , 8 word page read 40 mhz 6 9 ma v il input low voltage v cc = 2.7 to 3.6 v ?0.5 0.8 v v ih input high voltage v cc = 2.7 to 3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% ( 6 )8.59.5v v ol output low voltage i ol = 100 a, v cc =v cc min ( 6 )0.1v v oh output high voltage i oh = ?100 a ( 6 )v cc ?0.2 v v lko low v cc lock-out voltage ( 5 )2.32.5v
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 59 data sheet (preliminary) 11.8 ac characteristics 11.8.1 read operations notes 1. not 100% tested. 2. see figure 11.3 on page 55 and table 11.1 on page 55 for test specifications 3. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . 4. for 70pf output load capacitance, 2 ns is added to the above t acc ,t ce ,t pac c ,t oe values for all speed grades 5. ce1# and ce2# for the pl129n. 11.8.2 read operati on timing diagrams figure 11.6 read operation timings parameter description (notes) test setup speed options unit jedec std. 65 70 80 t avav t rc read cycle time ( 1 ) min 65 70 80 ns t avqv t acc address to output delay ce#, oe# = v il max657080 ns t elqv t ce chip enable to output delay ( 5 ) oe# = v il max657080 ns t pac c page access time max 25 30 30 ns t glqv t oe output enable to output delay max 25 30 30 ns t ehqz t df chip enable to output high z ( 3 ) max 16 ns t ghqz t df output enable to output high z ( 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first ( 3 ) min 5 ns t oeh output enable hold time ( 1 ) read min 0 ns toggle and data# polling min 10 ns t oh t ce data we# addresses ce# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
60 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) figure 11.7 page read operation timings 11.8.3 hardware reset (reset#) note not 100% tested. figure 11.8 reset timings same page addresses a 22 to a 3 output t ce t acc aa aa+1 aa+2 aa+3 aa+4 aa+5 aa+6 aa+7 t oe t oeh t pacc high-z t oh da da+1 da+2 da+7 t df da+3 da+4 da+5 da+6 t oh t oh t oh t oh t oh t oh t oh t pacc t pacc t pacc t pacc t pacc t pacc a 2 to a 0 ce# oe# we# parameter description all speed options unit jedec std. t rp reset# pulse width min 30 s t rh reset high time before read (see note) min 200 ns reset# t rp ce#, oe# t rh
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 61 data sheet (preliminary) 11.8.4 erase/program timing notes 1. not 100% tested. 2. in program operation timing, addresses are latched on the falling edge of we#. 3. see program/erase operations on page 25 for more information. 4. does not include the preprogramming time. parameter description (notes) speed options unit jedec std 65 70 80 t avav t wc write cycle time ( 1 ) min 65 70 80 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 35 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 40 ns t whdl t wph write pulse width high min 25 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation typ 40 s t whwh1 t whwh1 accelerated programming operation typ 24 s t whwh2 t whwh2 sector erase operation typ 1.6 sec t vhh v hh rise and fall times min 250 ns t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns t wep noise pulse margin on we# max 3 ns t sea sector erase accept time-out max 50 s t esl erase suspend latency max 20 s t psl program suspend latency max 20 s t asp toggle time during sector protection typ 100 s t psp toggle time during programming within a protected sector typ 1 s
62 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) figure 11.9 program operation timings note pa = program address, pd = program data, d out is the true data at the program address figure 11.10 accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 63 data sheet (preliminary) figure 11.11 chip/sector erase operation timings note sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 37 ) figure 11.12 back-to-back read/w rite cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t ce t ah valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as
64 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) figure 11.13 data# polling timings (during embedded algorithms) note va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read c ycle figure 11.14 toggle bit timings (during embedded algorithms) note va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read cy cle, and array data read cycle figure 11.15 dq2 vs. dq6 note dq2 toggles only when read at an address within an erase-suspended se ctor. the system may use oe# or ce# to toggle dq2 and dq6. we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 65 data sheet (preliminary) 11.8.5 erase and programming performance notes 1. typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 10,000 cycles. additionally, programming typicals assume checkerboard pattern. all values are subject to change. 2. under worst case conditions of 90c, v cc = 2.7 v, 100,000 cycles. all values are subject to change. 3. the typical chip programming time is consi derably less than the maximum chip programming time listed, since most bytes progra m faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 12.1 on page 66 and table 12.2 on page 68 for further information on command definitions. 6. contact the local sales office for minimum cycling endurance values in specific applicat ions and operating conditions. 7. see application note erase suspend/resume timing for more details. 8. word programming specification is ba sed upon a single word programming operation not utilizing the write buffer. 11.8.6 bga ball capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter (notes) device condition typ (note 1) max (note 2) unit comments (notes) sector erase time 128 kword v cc 1.6 7 s excludes 00h programming prior to erasure ( 4 ) acc 1.6 7 32 kword v cc 0.3 4 acc 0.3 4 chip erase time v cc 202 (pl256n) 100 (pl127n) 100(pl129n) 900 (pl256n) 450 (pl127n) 450 (pl129n) s acc 130 (pl256n) 65 (pl127n) 65 (pl129n) 512 (pl256n) 256 (pl127n) 256 (pl129n) word programming time v cc 40 400 s excludes system level overhead ( 5 ) acc 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 s acc 6 60 total 32-word buffer programming time v cc 300 3000 s acc 192 1920 chip programming time using 32-word buffer ( 3 ) v cc 157.3 (pl256n) 78.6 (pl127n) 78.6 (pl129n) 315 (pl256n) 158 (pl127n) 158 (pl129n) s excludes system level overhead ( 5 ) acc 100 (pl256n) 50 (pl127n) 50 (pl129n) 200 (pl256n) 100 (pl127n) 100 (pl129n) erase suspend/erase resume <20 s program suspend/program resume <20 s parameter parameter description test setup typ max unit c in input capacitance v in = 0 7 10 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v in = 0 8 11 pf
66 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 12. appendix this section contains information relating to softwar e control or interfacing with the flash device. for additional information and assistance regarding software, see additional resources on page 17 , or explore the web at www.spansion.com . legend x = don?t care. ra = read address. rd = read data. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse whichever hap pens later. pd = program data. data latches on the rising edg e of we# or ce# pulse, whichever occurs first. sa = sector address. pl127/129n = a22 ? a15; pl256n = a23 ? a15. ba = bank address. pl256n = a23 ? a21; pl127n = a22 ? a20; pl127n = a21 ? a20. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see table 7.1 on page 20 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: r ead cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the password verify command, and any cycle reading at rd(0) and rd(1). 4. data bits dq15 ? dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pwd3 ? pwd0. 5. unless otherwise noted, these address bits are don ? t cares: pl127: a22 ? a15; 129n: a21 ? a15; pl256n: a23 ? a14. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. table 12.1 memory array commands command sequence (notes) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read ( 7 ) 1 ra rd reset ( 8 ) 1 xxx f0 auto- select ( 9 ) manufacturer id 4 555 aa 2aa 55 [ba]555 90 [ba]x00 0001 device id ( 10 ) 6 555 aa 2aa 55 [ba]555 90 [ba]x01 227e [ba]x0e ( 10 ) [ba]x0f 2200 indicator bits 4 555 aa 2aa 55 [ba]555 90 [ba]x03 ( 11 ) program 4 555 aa 2aa 55 555 a0 pa data write to buffer ( 17 ) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( 17 ) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend ( 14 )1bab0 program/erase resume ( 15 )1ba30 cfi query ( 16 )1[ba]55598 unlock bypass mode unlock bypass entry 3 555 aa 2aa 55 555 20 unlock bypass program ( 12 , 13 ) 2 xx a0 pa pd unlock bypass sector erase ( 12 , 13 )2 xx 80sa 30 unlock bypass erase ( 12 , 13 )2xx80xxx10 unlock bypass cfi ( 12 , 13 )1ba98 unlock bypass reset 2 xx 90 xxx 00 secured silicon sector command definitions secured silicon sector secured silicon sector entry ( 18 ) 3 555 aa 2aa 55 555 88 secured silicon sector program 2 xx a0 pa data secured silicon sector read 1 ra data secured silicon sector exit ( 19 ) 4 555 aa 2aa 55 555 90 xx 00
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 67 data sheet (preliminary) 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspe nd) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address. see autoselect on page 23. 10. device ids: pl256n = 223ch; pl127n = 2220h; pl129n = 2221h. 11. see autoselect on page 23. 12. the unlock bypass command sequence is required prior to this command sequence. 13. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the max imum number of cycles in the command sequence is 37. 17. command sequence resets device for next command after write-to-buffer operation. 18. entry commands are needed to enter a specific mode to enable instructions only available within that mode. 19. the exit command must be issued to reset the device into read mode. otherwise the device hangs. 20. the following mode cannot be performed at the same time . autoselect/cfi/unlock bypass/secured silicon. command sequence rese ts device for next command after write-to-buffer operation. 21. command is valid when device is ready to read array data or when device is in autoselect mode. address equals 55h on all fut ure devices, but 555h for pl256n. 22. requires entry command sequence prior to execution. secured silico n sector exit reset command is required to exit this mode; device may otherwise be placed in an unknown state.
68 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) legend x = don?t care ra = read address. rd = read data. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse whichever hap pens later. pd = program data. data latches on the rising edg e of we# or ce# pulse, whichever occurs first. sa = sector address. pl127/129n = a22 ? a15; pl256n = a23 ? a15 ba = bank address. pl256n = a23 ? a21; pl127n = a22 ? a20; pl127n = a21 ? a20. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. pwd3 ? pwd0 = password data. pd3 ? pd0 present four 16 bit combinations that represent the 64-bit password rd(0) = dq0 protection indicator bit. if protected, dq0 = 0, if unprotected, dq0 = 1. table 12.2 sector protection commands command sequence (notes) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data lock register command set definitions lock register lock register command set entry ( 25 ) 3 555 aa 2aa 55 555 40 lock register bits program ( 26 ) 2 xx a0 00 data lock register bits read 1 00 data lock register command set exit ( 27 ) 2xx 90 xx 00 password protection command set definitions password password protection command set entry ( 25 ) 3 555 aa 2aa 55 555 60 password program 2 xx a0 00/01 02/03 pwd0/ pwd1/ pwd2/ pwd3 password read 4 00 pwd 0 01 pwd1 02 pwd2 03 pwd3 password unlock 7 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 00 29 password protection command set exit ( 27 ) 2xx 90 xx 00 non-volatile sector protection command set definitions ppb non-volatile sector protection command set entry ( 25 ) 3 555 aa 2aa 55 [ba]555 c0 ppb program 2 xx a0 [ba]sa 00 all ppb erase ( 22 ) 2 xx 80 00 30 ppb status read 1 [ba]sa rd(0) non-volatile sector protection command set exit ( 27 ) 2xx 90 xx 00 global non-volatile sector protection freeze command set definitions ppb lock bit global volatile sector protection freeze command set entry ( 25 ) 3 555 aa 2aa 55 555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 ba rd(0) global volatile sector protection freeze command set exit ( 27 ) 2xx 90 xx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry ( 25 ) 3 555 aa 2aa 55 [ba]555 e0 dyb set 2 xx a0 [ba]sa 00 dyb clear 2 xx a0 [ba]sa 01 dyb status read 1 [ba]sa rd(0) volatile sector protection command set exit ( 27 ) 2xx 90 xx 00
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 69 data sheet (preliminary) notes 1. see table 7.1 on page 20 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cyc le, fourth through sixth cycles of the autoselect commands, and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15 ? dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pwd3 ? pwd0. 5. unless otherwise noted, these address bits are don ? t cares: pl127: a22 ? a15; 129n: a21 ? a15; pl256n: a23 ? a14. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspe nd) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address. see autoselect on page 23. 10. the data is 0000h for an unlocked sector and 0001h for a locked sector. 11. device ids: pl256n = 223ch; pl127n = 2220h; pl129n = 2221h. 12. see autoselect on page 23. 13. the unlock bypass command sequence is required prior to this command sequence. 14. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode.the s ystem may read and program in non-erasing sectors, or enter the autoselect mode, when in t he erase suspend mode. the erase suspend command is valid only d uring a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. command is valid when device is ready to read array data or when device is in autoselect mode.the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 17. the entire four bus-cycle sequence must be entered for which portion of the password. 18. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode.the s ystem may read and program in non-erasing sectors, or enter the autoselect mode, when in t he erase suspend mode. the erase suspend command is valid only d uring a sector erase operation, and requires the bank address. 19. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 20. command is valid when device is ready to read array data or when device is in autoselect mode.the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 21. the entire four bus-cycle sequence must be entered for which portion of the password. 22. the all ppb erase command pre-programs all ppbs be fore erasure to prevent over-erasure of ppbs. 23. wp#/acc must be at vhh during the entire operation of this command. 24. command sequence resets device for next command after write-to-buffer operation. 25. entry commands are needed to enter a specific mode to enable instructions only available within that mode. 26. if both the persistent protection mode locking bit and the pass word protection mode locking bit are set a the same time, the command operation aborts and returns the device to the default persistent sector protection mode. 27. the exit command must be issued to reset the device into read mode. otherwise the device hangs.
70 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) 13. common flash memory interface the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified soft -ware algorithms to be used for entire families of devices. software support can then be device-in dependent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device fam ilies. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address (ba)555h any time the device is ready to read arra y data. the system can read cfi information at the addresses given in tables 12.3 ? 12.6 ) within that bank. all reads outside of the cfi address range, within the bank, return non-valid data. reads from other banks ar e allowed, writes are not. to terminate reading cfi data, the system must wr ite the reset command. the following is a c source code example of using the cfi entry and exit f unctions. refer to the spansion low level driver user?s guide (available at www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *((uint16 *)bank_addr + 0x555) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *((uint16 *)bank_addr + 0x000) = 0x00f0; /* write cfi exit command */ for further information, please see the cfi spec ification (see jedec publications jep137-a and jesd68.01and cfi publication 100). please contact yo ur sales office for copi es of these documents. table 13.1 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 71 data sheet (preliminary) table 13.2 system interface string addresses data description 1bh 0027h v cc min. (write/erase) d7 ? d4: volt, d3 ? d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7 ? d4: volt, d3 ? d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0006h typical timeout per single byte/word write 2 n s 20h 0009h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000bh typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0003h max. timeout for byte/word write 2 n times typical 24h 0003h max. timeout for buffer write 2 n times typical 25h 0002h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 13.3 device geometry definition addresses data description 27h 0019h (pl256n) 0018h (pl127n) 0018h (pl129n) device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (see cfi publication 100) 2ah 2bh 0006h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0000h 0001h erase block region 1 information (see the cfi specificati on or cfi publication 100) 31h 007dh (pl256n) 003dh (pl127n) 003dh (pl129n) erase block region 2 information (see the cfi specificati on or cfi publication 100) 32h 33h 34h 0000h 0000h 0004h 35h 36h 37h 38h 0003h 0000h 0000h 0001h erase block region 3 information (see the cfi specificati on or cfi publication 100)
72 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) table 13.4 primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major version number, ascii (reflects modifications to the silicon) 44h 0034h minor version number, ascii (reflects modifications to the cfi table) 45h 0010h address sensitive unlock (bits 1 ? 0) 0 = required, 1 = not required silicon technology (bits 5 ? 2) 0100 = 0.11 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h (pl-n) sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800 mode 07 = new sector protect mode, 08 = advanced sector protection 4ah 0073h (pl256n) 003bh (pl127n) 003bh (pl129n) simultaneous operation 00 = not supported, x = number of sectors except bank a 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h (pl-n) page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7 ? d4: volt, d3 ? d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7 ? d4: volt, d3 ? d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = no boot, 01h = dual boot device, 02h = bottom boot device, 03h = top boot device 50h 0001h program suspend 0 = not supported, 1 = supported 51h 0001h unlock bypass 00 = not supported, 01=supported 52h 0007h secured silicon sector (customer otp area) size 2 n bytes 53h 000fh hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns 54h 000eh hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend time-out maximum 2 n s 56h 0005h program suspend time-out maximum 2 n s 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0013h (pl256n) 000bh (pl127n) 000bh (pl129n) bank a region information. x = number of sectors in bank 59h 0030h (pl256n) 0018h (pl127n) 0018h (pl129n) bank 1 region information. x = number of sectors in bank 5ah 0030h (pl256n) 0018h (pl127n) 0018h (pl129n) bank 2 region information. x = number of sectors in bank 5bh 0013h (pl256n) 000bh (pl127n) 000bh (pl129n) bank 3 region information. x = number of sectors in bank
june 6, 2007 s29pl-n_00_a5 s29pl-n mirrorbit ? flash family 73 data sheet (preliminary) 14. revision history section description revision a0 (february 28, 2005) initial release revision a1 (august 8, 2005) performance characteristics updated package options mcp look-ahead connection diagram corrected pinout memory map added sector and memory address map for s29pl127n device operation table added dual chip enable device operation table v cc power up updated t vcs . added v cc ramp rate restriction dc characteristics updated ty pical and maximum values. revision a2 (october 25, 2005) ordering information updated table connection diagram and package dimensions - s29pl-n fortified bga added pinout and package dimensions. global changed data sheet status from advance information to preliminary. removed byte address information distinctive and performance characteristics removed enhanced versatilei/o, updated r ead access times, and package options. logic symbol and block diagram removed v io from logic symbol and block diagram. erase and programming performance updated table write buffer programming updated write buffer abort description. operating ranges updated v io supply voltages. dc characteristics updated i cc1 , i cc4 , i cc6 . revision a3 (november 14, 2005) ordering information updated table valid combinations table updated table revision a4 (november 23, 2005) logic symbols removed v io from the illustrations block diagram removed v io from the illustration connection diagrams modified fortified bga pinout (laa064) pl129n sector and memory address map updated address ranges for banks 2a and 2b revision a5 (june 6, 2007) global removed laa064 package offering and all relevant ordering information
74 s29pl-n mirrorbit ? flash family s29pl-n_00_a5 june 6, 2007 data sheet (preliminary) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2005-2007 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , hd-sim ? and combinations thereof, are trademarks of spansion llc in the us and other countries . other names used are for informational purposes only and may be trademarks of their respective owners.

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